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ZL50052
8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs Data Sheet Features
* 8,192 channel x 8,192 channel non-blocking unidirectional switching. The Backplane and Local inputs and outputs can be combined to form a non-blocking switching matrix with 16 input streams and 16 output streams 4,096 channel x 4,096 channel non-blocking Backplane input to Local output stream switch 4,096 channel x 4,096 channel non-blocking Local input to Backplane output stream switch 4,096 channel x 4,096 channel non-blocking Backplane input to Backplane output switch 4,096 channel x 4,096 channel non-blocking Local input to Local output stream switch Backplane port accepts 8 input and 8 output STBUS streams with data rate of 32.768 Mbps Local port accepts 8 input and 8 output ST-BUS streams with data rate of 32.768 Mbps Exceptional input clock jitter tolerance (14 ns) Per-stream bit delay for Local and Backplane input streams Per-stream advancement for Local and Backplane output streams * * * * * * * Ordering Information ZL50052GAC 196 ball PBGA
December 2003
* * * * * * * * *
-40C to +85C Constant 2-frame throughput delay for frame integrity Per-channel high impedance output control for Local and Backplane streams Per-channel driven-high output control for Local and Backplane streams Per-channel message mode for Local and Backplane output streams Connection memory block programming for fast device initialization Automatic selection between ST-BUS and GCIBus operation Non-multiplexed Motorola microprocessor interface
VDD_IO VDD_CORE
VSS (GND)
RESET
ODE
BSTi0-7
Backplane Data Memories (4,096 channels)
Local Interface
LSTi0-7
Backplane Interface BSTo0-7
Backplane Connection Memory (4,096 locations)
Local Connection Memory (4,096 locations)
Local Interface LSTo0-7
BORS
Local Data Memories (4,096 channels)
LORS
FP8i
Input Timing Unit
Output Timing Unit
FP8o FP16o C8o C16o
C8i
PLL
Microprocessor Interface and Internal Registers
Test Port
VDD_PLL
DS CS R/W
A14-0
DTA
D15-0
TMS TDi TDo TCK TRST
Figure 1 - ZL50052 Functional Block Diagram 1
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ZL50052
* * * * * Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard Memory Built-In-Self-Test (BIST), controlled via microprocessor register 1.8 V core supply voltage 3.3 V I/O supply voltage 5 V tolerant inputs, outputs and I/Os
Data Sheet
Applications
* * * * * * Central Office Switches (Class 5) Media Gateways Class-Independent Switches Access Concentrators Scalable TDM-Based Architectures Digital Loop Carriers
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Zarlink Semiconductor Inc.
ZL50052
Device Overview
Data Sheet
The ZL50052 has two data ports, the Backplane and the Local port. Both the Backplane and Local ports operate at 32.768 Mbps. The ZL50052 contains two data memory blocks (Backplane and Local) to provide the following switching path configurations: * * * * * Input-to-Output Unidirectional, supporting 8 K x 8 K switching Backplane-to-Local Bi-directional, supporting 4 K x 4 K data switching Local-to-Backplane Bi-directional, supporting 4 K x 4 K data switching Backplane-to-Backplane Bi-directional, supporting 4 K x 4 K data switching Local-to-Local Bi-directional, supporting 4 K x 4 K data switching
The device contains two connection memory blocks, one for the Backplane output and one for the Local output. Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly from the connection memory contents (Message Mode). In Connection Mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel, (stored in data memory), to be switched. In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output streams on a per-channel basis. This feature is useful for transferring control and status information to external circuits or other ST-BUS devices. The device uses a master frame pulse (FP8i) and master clock (C8i) to define the input frame boundary and timing for both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a GCIBus style frame pulse is being used. There is a two-frame delay from the time RESET is de-asserted to the establishment of full switch functionality. During this period, the input frame pulse format is determined before switching begins. The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the outputs of the Backplane and Local ports. A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and switching configurations. The microprocessor port provides access for Register read/write, Connection Memory read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and four control signals. The microprocessor may monitor channel data in the Backplane and Local data memories. The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port. The ZL50052 is available in one package: * a 15 mm x 15 mm body, 1 mm ball-pitch, 196-PBGA
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ZL50052 Table of Contents
Data Sheet
1.0 Unidirectional and Bi-directional Switching Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1 Flexible Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.1.1 Non-Blocking Unidirectional Configuration (Typical System Configuration) . . . . . . . . . . . . . . . . . . 14 1.1.2 Non-Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.1.3 Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 Switching Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.1 Unidirectional Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.2 Backplane-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.3 Local-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.4 Backplane-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.5 Local-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.6 Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.6.1 Local Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.6.2 Backplane Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 Frame Pulse Input and Master Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 Input Frame Pulse and Generated Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4 Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 Input Clock Jitter Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.0 Input and Output Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Input Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.1 Input Bit Delay Programming (Backplane and Local Input Streams) . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 Output Advancement Programming (Backplane and Local Output Streams) . . . . . . . . . . . . . . . . . . . . . . 20 4.0 Port High-Impedance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.0 Device Power-Up, Initialization and Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.0 Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.1 Local Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.2 Backplane Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.3 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.3.1 Memory Block Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.0 Memory Built-In-Self-Test (BIST) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.2 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.2.1 Test Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.2.2 Test Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.2.2.3 The Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.3 Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.0 Memory Address Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.1 Local Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.2 Backplane Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.3 Local Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.4 Backplane Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 12.0 Internal Register Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 13.0 Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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ZL50052 Table of Contents
Data Sheet
13.1 Control Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 13.2 Block Programming Register (BPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 13.3 Local Input Bit Delay Registers (LIDR0 to LIDR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 13.3.1 Local Input Delay Bits 4-0 (LID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 13.4 Backplane Input Bit Delay Registers (BIDR0 to BIDR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 13.4.1 Backplane Input Delay Bits 4-0 (BID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 13.5 Local Output Advancement Registers (LOAR0 to LOAR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 13.5.1 Local Output Advancement Bits 1-0 (LOA1-LOA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 13.6 Backplane Output Advancement Registers (BOAR0 - BOAR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.6.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.7 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.8 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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ZL50052 List of Figures
Data Sheet
Figure 1 - ZL50052 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50052 PBGA Connections (196 PBGA, 15 mm x 15 mm) Pin Diagram (as viewed through top of package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3 - 8,192 x 8,192 Channels (32 Mbps), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4 - 4,096 x 4,096 Channels (32 Mbps), Bi-directional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5 - 6,144 x 2,048 Channels Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6 - ST-BUS and GCI-Bus Input Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7 - Input and Output (Generated) Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 32 Mbps . . . . . . . . . . . . . . . . . 19 Figure 9 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for Data Rate of 32 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 10 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 32 Mbps . . . . . . . . . . . 21 Figure 11 - Data Throughput Delay with Input Ch0 Switched to Output Ch0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 12 - Data Throughput Delay with Input Ch0 Switched to Output Ch13. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 13 - Data Throughput Delay with Input Ch13 Switched to Output Ch0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 14 - Hardware RESET De-assertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 15 - Frame Boundary Conditions, ST-BUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 16 - Frame Boundary Conditions, GCI-Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 17 - Input and Output Clock Timing Diagram for ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 18 - Input and Output Clock Timing Diagram for GCI-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 19 - ST-BUS Local/Backplane Data Timing Diagram (32 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 20 - GCI-Bus Local/Backplane Data Timing Diagram (32 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 21 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 22 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 23 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 24 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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ZL50052 List of Tables
Data Sheet
Table 1 - Local and Backplane Output Enable Control Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 2 - Local and Backplane Connection Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 3 - Local Connection Memory in Block Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 4 - Backplane Connection Memory in Block Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 5 - Address Map for Data and Connection Memory Locations (A14 = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 6 - Local Data Memory (LDM) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 7 - Backplane Data Memory (BDM) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 8 - LCM Bits for Source-to-Local Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 9 - BCM Bits for Source-to-Backplane Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 10 - Address Map for Registers (A14 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 11 - Control Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 12 - Block Programming Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 13 - Local Input Bit Delay Register (LIDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 14 - Local Input Bit Delay and Sampling Point Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 15 - Backplane Input Bit Delay Register (BIDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 16 - Backplane Input Bit Delay and Sampling Point Programming Table. . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 17 - Local Output Advancement Register (LOAR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 18 - Local Output Advancement (LOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 19 - Backplane Output Advancement Register (BOAR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 20 - Backplane Output Advancement (BOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 21 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 22 - Device Identification Register (DIR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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Zarlink Semiconductor Inc.
ZL50052
Pinout Diagram: (as viewed through top of package) A1 corner identified by metallized marking, mold indent, ink dot, or right-angled corner.
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Data Sheet
A
BSTo1
BSTo2
A4
A5
A8
A9
A12
A13
R/W
CS
TMS
TDo
IC_ OPEN LSTo0
TRST
B
A0
BSTo5
BSTo0
A1
A2
A7
A11
A14
ODE
TDi
TCK
IC_ OPEN IC_ OPEN LSTo4
LSTo1
C
IC_GND BSTo7
IC_ OPEN IC_ OPEN IC_ OPEN IC_ OPEN VDD_ CORE BSTi3
BSTo3
BSTo4
A6
A10
DS
RESET
IC_ OPEN VDD_IO
IC_GND
IC_GND
LSTo3
D
IC_GND BSTo6
GND
A3
VDD_IO VDD_IO VDD_IO
DTA
GND
LSTo6
LSTo2
E
IC_ OPEN IC_ OPEN BSTi0
IC_ OPEN IC_ OPEN BORS
VDD_IO
GND
VDD_ CORE GND
VDD_ CORE GND
VDD_ CORE GND
VDD_ CORE GND
GND
VDD_IO
IC_ OPEN IC_ OPEN IC_ OPEN VDD_ CORE LSTi5
LSTo7
LSTo5
F
VDD_IO
VDD_ CORE VDD_ CORE VDD_ CORE VDD_ CORE GND
VDD_ CORE VDD_ CORE VDD_ CORE VDD_ CORE GND
VDD_IO
IC_ OPEN IC_ OPEN LORS
IC_ OPEN IC_ OPEN IC_ OPEN LSTi2
G
VDD_IO
GND
GND
GND
GND
VDD_IO
H
BSTi1
BSTi2
VDD_IO
GND
GND
GND
GND
VDD_IO
J
BSTi4
BSTi5
BSTi7
VDD_IO
GND
GND
GND
GND
VDD_IO
LSTi1
K
BSTi6
IC_ OPEN IC_ OPEN IC_ OPEN D13
IC_ OPEN IC_ OPEN D15
VDD_IO
VDD_ CORE
VDD_ CORE
VDD_ CORE
VDD_ CORE
VDD_IO
IC_ OPEN IC_ OPEN IC_ OPEN IC_ OPEN FP16o
LSTi3
LSTi0
L
IC_ OPEN IC_ OPEN IC_ OPEN GND
GND
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
GND
IC_ OPEN LSTi7
LSTi6
M
D14
D12
D5
IC_GND IC_GND
C16o
FP8i
IC_ OPEN FP8o
LSTi4
N
D10
D11
D7
D3
D0
IC_GND
VDD_ PLL IC_ OPEN
C8o
IC_ OPEN GND
IC_ OPEN GND
P
D9
D8
D6
D4
D2
D1
IC_GND
C8i
IC_ OPEN
Figure 2 - ZL50052 PBGA Connections (196 PBGA, 15 mm x 15 mm) Pin Diagram
(as viewed through top of package)
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Zarlink Semiconductor Inc.
ZL50052
Pin Description ZL50052 Package Coordinates (196 ball PBGA)
Data Sheet
Pin Name
Description
Device Timing C8i P10
Master Clock (5 V Tolerant Schmitt-Triggered Input) This pin accepts an 8.192 MHz clock. The internal frame boundary is aligned with the clock falling or rising edge, as controlled by the C8IPOL bit in the Control Register. Input data on both the Backplane and Local sides (BSTi0-7 and LSTi0-7) must be aligned to this clock and the accompanying input frame pulse, FP8i. Frame Pulse Input (5 V Tolerant Schmitt-Triggered Input) When the Frame Pulse Width bit (FPW) of the Control Register is LOW (default), this pin accepts a 122 ns-wide frame pulse. When the FPW bit is HIGH, this pin accepts a 244 ns-wide frame pulse. The device will automatically detect whether an ST-BUS or GCI-Bus style frame pulse is applied. Input data on both the Backplane and Local sides (BSTi0-7 and LSTi0-7) must be aligned to this frame pulse and the accompanying input clock, C8i. C8o Output Clock (5 V Tolerant Three-state Output) This pin outputs an 8.192 MHz clock generated within the device. The clock falling edge or rising edge is aligned with the output frame boundary presented on FP8o; this edge polarity alignment is controlled by the COPOL bit of the Control Register. Output data on both the Backplane and Local sides (BSTo0-7 and LSTo0-7) will be aligned to this clock and the accompanying output frame pulse, FP8o. Frame Pulse Output (5 V Tolerant Three-state Output) When the Frame Pulse Width bit (FPW) of the Control Register is LOW (default), this pin outputs a 122 ns-wide frame pulse. When the FPW bit is HIGH, this pin outputs a 244 ns-wide frame pulse. The frame pulse, running at 8 kHz rate, will have the same format (ST-BUS or GCI-Bus) as the input frame pulse (FP8i). Output data on both the Backplane and Local sides (BSTo0-7 and LSTo0-7) will be aligned to this frame pulse and the accompanying output clock, C8o. C16o Output Clock (5 V Tolerant Three-state Output) This pin outputs a 16.384 MHz clock generated within the device. The clock falling edge or rising edge is aligned with the output frame boundary presented on FP16o; this edge polarity alignment is controlled by the COPOL bit of the Control Register. Output data on both the Backplane and Local sides (BSTo0-7 and LSTo0-7) will be aligned to this clock and the accompanying output frame pulse, FP16o.
FP8i
M10
C8o
N10
FP8o
N11
C16o
M9
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Zarlink Semiconductor Inc.
ZL50052
Pin Description (continued) ZL50052 Package Coordinates (196 ball PBGA)
P12
Data Sheet
Pin Name
Description
FP16o
Frame Pulse Output (5 V Tolerant Three-state Output) When the Frame Pulse Width bit (FPW) of the Control Register is LOW (default), this pin outputs a 61 ns-wide frame pulse. When the FPW bit is HIGH, this pin outputs a 122 ns-wide frame pulse. The frame pulse, running at 8 kHz rate, will have the same format (ST-BUS or GCI-Bus) as the input frame pulse (FP8i). Output data on both the Backplane and Local sides (BSTo0-7 and LSTo0-7) will be aligned to this frame pulse and the accompanying output clock, C16o.
Backplane and Local Inputs
BSTi0-7
G1, H1, H2, H3, J1, J2, K1, J3
Backplane Serial Input Streams 0 to 7 (5 V Tolerant Inputs with Internal Pull-downs) These pins accept serial TDM data streams at a fixed data rate of 32.768 Mbps (with 512 channels per stream). Local Serial Input Streams 0 to 7 (5 V Tolerant Inputs with Internal Pull-downs) These pins accept serial TDM data streams at a fixed data rate of 32.768 Mbps (with 512 channels per stream).
LSTi0-7
K14, J13, J14, K13, M14, J12, L14, M13
Backplane and Local Outputs and Control
ODE
B9
Output Drive Enable (5 V Tolerant Input with Internal Pull-up) An asynchronous input providing Output Enable control to the BSTo0-7 and LSTo0-7 outputs. When LOW, the BSTo0-7 and LSTo0-7 outputs are driven HIGH or high impedance (dependent on the BORS and LORS pin settings respectively). When HIGH, the outputs BSTo0-7 and LSTo0-7 are enabled.
BORS
G2
Backplane Output Reset State (5 V Tolerant Input with Internal Pull-down) When this input is LOW, the device will initialize with the BSTo0-7 outputs driven high. Following initialization, the Backplane stream outputs are always active. When this input is HIGH, the device will initialize with the BSTo0-7 outputs at high impedance. Following initialization, the Backplane stream outputs may be set active or high impedance using the ODE pin or on a per-channel basis with the BE bit in the Backplane Connection Memory.
BSTo0-7
B3, A1, A2, C4, C5, B2, D2, C2
Backplane Serial Output Streams 0 to 7 (5 V Tolerant, Three-state Outputs with Slew-Rate Control) These pins output serial TDM data streams at a fixed data rate of 32.768 Mbps (with 512 channels per stream). Refer to the descriptions of the BORS and ODE pins for control of the output HIGH or high impedance state.
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Zarlink Semiconductor Inc.
ZL50052
Pin Description (continued) ZL50052 Package Coordinates (196 ball PBGA) H13
Data Sheet
Pin Name
Description
LORS
Local Output Reset State (5 V Tolerant Input with Internal Pull-down) When this input is LOW, the device will initialize with the LSTo0-7 outputs driven high. Following initialization, the Local stream outputs are always active. When this input is HIGH, the device will initialize with the LSTo0-7 outputs at high impedance. Following initialization, the Local stream outputs may be set active or high impedance using the ODE pin or on a per-channel basis with the LE bit in the Local Connection Memory.
LSTo0-7
B13, B14, D14, C14, D12, E14, D13, E13
Local Serial Output Streams 0 to 7 (5 V Tolerant Three-state Outputs with Slew-Rate Control) These pins output serial TDM data streams at a fixed data rate of 32.768 Mbps (with 512 channels per stream). Refer to the descriptions of the LORS and ODE pins for control of the output HIGH or high impedance state.
Microprocessor Port Signals
A0 - A14
B1, B4, B5, D5, A3, A4, C6, B6, A5, A6, C7, B7, A7, A8, B8 N7, P7, P6, N6, P5, M6, P4, N5, P3, P2, N3, N4, M5, N2, M4, M3 A10
Address 0 - 14 (5 V Tolerant Inputs) These pins form the 15-bit address bus to the internal memories and registers.
A0 = LSB
D0 - D15
Data Bus 0 - 15 (5 V Tolerant Inputs/Outputs with Slew-Rate Control) These pins form the 16-bit data bus of the microprocessor port. D0 = LSB Chip Select (5 V Tolerant Input) Active LOW input used by the microprocessor to enable the microprocessor port access Note that a minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion of CS and/or DS to initiate the next access. Data Strobe (5 V Tolerant Input) This active LOW input works in conjunction with CS to enable the microprocessor port read and write operations. Note that a minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion of CS and/or DS to initiate the next access. Read/Write (5 V Tolerant Input) This input controls the direction of the data bus lines (D0-D15) during a microprocessor access. Data Transfer Acknowledgment (5 V Tolerant Three-state Output) This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required to hold a HIGH level. Note that a minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion of CS and/or DS to initiate the next access.
CS
DS
C8
R/W
A9
DTA
D9
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Zarlink Semiconductor Inc.
ZL50052
Pin Description (continued) ZL50052 Package Coordinates (196 ball PBGA) C9
Data Sheet
Pin Name
Description
RESET
Device Reset (5 V Tolerant Input with Internal Pull-up) This input (active LOW) asynchronously applies reset and synchronously releases reset to the device. In the reset state, the outputs LSTo0-7 and BSTo0-7 are set to a HIGH or high impedance state, depending on the state of the LORS and BORS external control pins, respectively. The assertion of this pin also clears the device registers and internal counters. Refer to Section 7.3 on page 24 for the timing requirements regarding this reset signal.
JTAG Control Signals TCK TMS TDi TDo B11 A11 B10 A12 Test Clock (5 V Tolerant Input) Provides the clock to the JTAG test logic. Test Mode Select (5 V Tolerant Input with Internal Pull-up) JTAG signal that controls the state transitions of the TAP controller. Test Serial Data In (5 V Tolerant Input with Internal Pull-up) JTAG serial test instructions and data are shifted in on this pin. Test Serial Data Out (5 V Tolerant Three-state Output) JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in a high impedance state when JTAG is not enabled. Test Reset (5 V Tolerant Input with Internal Pull-up) Asynchronously initializes the JTAG TAP controller to the Test-Logic-Reset state. This pin must be pulsed LOW during power-up for JTAG testing. This pin must be held LOW for normal functional operation of the device.
TRST
A14
Power and Ground Pins VDD_IO D6, D7, D8, D10, E4, E11, F4, F11, G4, G11, H4, H11, J4, J11, K4, K11, L5, L6, L7, L8, L9, L10 E6, E7, E8, E9, F5, F10, G3, G5, G10, H5, H10, H12, J5, J10, K6, K7, K8, K9 N9
Power Supply for Periphery Circuits: +3.3 V
VDD_CORE
Power Supply for Core Circuits: +1.8 V
VDD_PLL
Power Supply for Analog PLL: +1.8 V
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Zarlink Semiconductor Inc.
ZL50052
Pin Description (continued) ZL50052 Package Coordinates (196 ball PBGA) D4, D11, E5, E10, F6, F7, F8, F9, G6, G7, G8, G9, H6, H7, H8, H9, J6, J7, J8, J9, K5, K10, L4, L11, P1, P13, P14
Ground
Data Sheet
Pin Name
Description
VSS (GND)
Unused Pins IC_OPEN A13, B12, C3, C10, C12, D3, E1, E2, E3, E12, F1, F2, F3, F12, F13, F14, G12, G13, G14, H14, K2, K3, K12, L1, L2, L3, L12, L13, M1, M2, M11, M12, N1, N12, N13, N14, P9, P11 C1, C11, C13, D1, M7, M8, N8, P8
Internal Connections - OPEN These pins must be left unconnected.
IC_GND
Internal Connections - GND These pins must be tied LOW.
1.0
Unidirectional and Bi-directional Switching Applications
The ZL50052 has a maximum capacity of 8,192 input channels and 8,192 output channels. This is calculated from the number of streams and channels: 16 input streams (8 Backplane, 8 Local) at 32.768 Mbps and 16 output streams (8 Backplane, 8 Local) at 32.768 Mbps, with each stream providing 512 channels. A typical mode of operation is to separate the input and output streams to form a unidirectional switch, as shown in Figure 3 below.
BSTi0-7 8 streams INPUT LSTi0-7 8 streams ZL50052
BSTo0-7 8 streams OUTPUT LSTo0-7 8 streams
Figure 3 - 8,192 x 8,192 Channels (32 Mbps), Unidirectional Switching
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Zarlink Semiconductor Inc.
ZL50052
Data Sheet
In this system, the Backplane and Local input streams are combined, and the Backplane and Local output streams are combined, so that the switch appears as a 16 input stream by 16 output stream switch. This gives the maximum 8,192 x 8,192 channel capacity. Often a system design needs to differentiate between a Backplane and a Local side, or it needs to put the switch in a bi-directional configuration. In this case, the ZL50052 can be used as shown in Figure 4 to give 4,096 x 4,096 channel bi-directional capacity.
BSTi0-7 8 streams BACKPLANE BSTo0-7 8 streams ZL50052
LSTo0-7 8 streams LOCAL LSTi0-7 8 streams
Figure 4 - 4,096 x 4,096 Channels (32 Mbps), Bi-directional Switching In this system setup, the chip has a capacity of 4,096 input channels and 4,096 output channels on the Backplane side, as well as 4,096 input channels and 4,096 output channels on the Local side. Note that some or all of the output channels on one side can come from the other side, e.g., Backplane input to Local output switching.
1.1
Flexible Configuration
The ZL50052 can be configured as an 8 K by 8 K non-blocking unidirectional digital switch, a 4 K by 4 K non-blocking bi-directional digital switch, or as a blocking switch with various switching capacities.
1.1.1
Non-Blocking Unidirectional Configuration (Typical System Configuration)
Because the input and output drivers are synchronous, the user can combine input Backplane streams and input Local streams as well as output Backplane streams and output Local streams to increase the total number of input and output streams of the switch in a unidirectional configuration, as shown in Figure 3. * 8,192 channel x 8,192 channel non-blocking switching from input to output streams
1.1.2
Non-Blocking Bi-directional Configuration
Another typical application is to configure the ZL50052 as a non-blocking 4 K by 4 K bi-directional switch, as shown in Figure 4: * * * * 4,096 channel x 4,096 channel non-blocking switching from Backplane input to Local output streams 4,096 channel x 4,096 channel non-blocking switching from Local input to Backplane output streams 4,096 channel x 4,096 channel non-blocking switching from Backplane input to Backplane output streams 4,096 channel x 4,096 channel non-blocking switching from Local input to Local output streams
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Zarlink Semiconductor Inc.
ZL50052
1.1.3 Blocking Bi-directional Configuration
Data Sheet
The ZL50052 can be configured as a blocking bi-directional switch if it is an application requirement. For example, it can be configured as a 6 K by 2 K bi-directional blocking switch, as shown in Figure 5: * * * * 6,144 channel x 2,048 channel blocking switching from Backplane input to Local output streams 2,048 channel x 6,144 channel blocking switching from Local input to Backplane output streams 6,144 channel x 6,144 channel non-blocking switching from Backplane input to Backplane output streams 2,048 channel x 2,048 channel non-blocking switching from Local input to Local output streams
ZL50052 BSTi0-7 LSTi0-3 BSTo0-7 LSTo0-3 6 K by 6 K 2 K by 6 K 6 K by 2 K 2 K by 2 K LSTi4-7 LSTo4-7
Total 12 streams input and 12 streams output
Total 4 streams input and 4 streams output
Figure 5 - 6,144 x 2,048 Channels Blocking Bi-directional Configuration
2.0
2.1
Functional Description
Switching Configuration
The device supports five switching configurations: 1. Unidirectional switch 2. Backplane-to-Local 3. Local-to-Backplane 4. Backplane-to-Backplane 5. Local-to-Local The following sections describe the switching paths in detail. Configurations (2) - (5) enable a non-blocking bi-directional switch with 4,096 Backplane input/output channels at Backplane stream data rates of 32.768 Mbps, and 4,096 Local input/output channels at Local stream data rates of 32.768 Mbps. The switching paths of configurations (2) to (5) may be operated simultaneously.
2.1.1
Unidirectional Switch
The device can be configured as a 8,192 x 8,192 unidirectional switch by grouping together all input streams and all output streams. All streams operate at a data rate of 32.768 Mbps.
2.1.2
Backplane-to-Local Path
The device can provide data switching between the Backplane input port and the Local output port. The Local Connection Memory determines the switching configurations.
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Zarlink Semiconductor Inc.
ZL50052
2.1.3 Local-to-Backplane Path
Data Sheet
The device can provide data switching between the Local input port and the Backplane output port. The Backplane Connection Memory determines the switching configurations.
2.1.4
Backplane-to-Backplane Path
The device can provide data switching between the Backplane input and output ports. The Backplane Connection Memory determines the switching configurations.
2.1.5
Local-to-Local Path
The device can provide data switching between the Local input and output ports. The Local Connection Memory determines the switching configurations.
2.1.6
Port Operation
The Local port has 8 input (LSTi0-7) and 8 output (LSTo0-7) data streams. Similarly, the Backplane port has 8 input (BSTi0-7) and 8 output (BSTo0-7) data streams. All the streams operate at 32.768 Mbps. The timing of the input and output clocks and frame pulses is shown in Figure 7, "Input and Output (Generated) Frame Pulse Alignment" on page 17. The input traffic are aligned based on the FP8i and C8i input timing signals, while the output traffic are aligned based on the FP8o and C8o output timing signals.
2.1.6.1
Local Output Port
Operation of stream data in Connection Mode or Message Mode is determined by the state of the LMM bit of the Local Connection Memory. The channel high impedance state is controlled by the LE bit of the Local Connection Memory. The data source (e.g., from the Local or Backplane Data Memory) is determined by the LSRC bit of the Local Connection Memory. Refer to Section 8.1, Local Connection Memory, and Section 11.3, Local Connection Memory Bit Definition for more details.
2.1.6.2
Backplane Output Port
Operation of stream data in Connection Mode or Message Mode is determined by the state of the BMM bit of the Backplane Connection Memory and the channel high impedance state is controlled by the BE bit of the Backplane Connection Memory. The data source (e.g., from the Local or Backplane Data Memory) is determined by the BSRC bit of the Backplane Connection Memory. Refer to Section 8.2, Backplane Connection Memory and Section 11.4, Backplane Connection Memory Bit Definition for more details.
2.2
Frame Pulse Input and Master Input Clock Timing
The input frame pulse (FP8i) is an 8 kHz input signal active for 122 ns or 244 ns at the frame boundary. The FPW bit in the Control Register must be set according to the applied pulse width. See Pin Description and Table 11, "Control Register Bits" on page 32 for details. The active state and timing of FP8i can conform either to the ST-BUS or to the GCI-Bus as shown in Figure 6, "ST-BUS and GCI-Bus Input Timing Diagram". The ZL50052 device will automatically detect whether an ST-BUS or a GCI-Bus style frame pulse is being used for the master frame pulse (FP8i). The output frame pulses (FP8o and FP16o) are always of the same style (ST-BUS or GCI-Bus) as the input frame pulse. The active edge of the input clock (C8i) shall be selected by the state of the Control Register bit C8IPOL. Note that the active edge of ST-BUS is falling edge, which is the default mode of the device, while GCI-Bus uses rising edge as the active edge. Although GCI frame pulse will be automatically detected, to fully conform to GCI-Bus operation, the device should be set to use C8i rising edge as the active edge (by setting bit C8IPOL HIGH) when GCI-Bus is used.
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Zarlink Semiconductor Inc.
ZL50052
Data Sheet
For the purposes of describing the device operation, the remaining part of this document assumes the ST-BUS frame pulse format with a single width frame pulse of 122ns and a falling active clock-edge, unless explicitly stated otherwise. In addition, the device provides FP8o, FP16o, C8o and C16o outputs to support external devices which connect to the output ports. The generated frame pulses (FP8o, FP16o) will be provided in the same format as the master frame pulse (FP8i). The polarity of C8o and C16o, at the frame boundary, can be controlled by the Control Register bit, COPOL. An analog phase lock loop (APLL) is used to multiply the input clock frequency on C8i to generate an internal clock signal operating at 131.072 MHz.
FP8i (ST-BUS) (8 kHz) C8i (ST-BUS) (8.192 MHz) FP8i (GCI-Bus) (8 kHz) C8i (GCI-Bus) (8.192 MHz)
Channel 0 Channel 1 Channel 510 Channel 511
BSTi/LSTi0-7 (32 Mbps) ST-BUS BSTi/LSTi0-7 (32 Mbps) GCI-Bus
32107654321076543210
65432107654321076 Channel 510 Channel 511
Channel 0
Channel 1
45670123456701234567
12345670123456701 Channel 255
Channel 0
Figure 6 - ST-BUS and GCI-Bus Input Timing Diagram
2.3
Input Frame Pulse and Generated Frame Pulse Alignment
The ZL50052 accepts a frame pulse (FP8i) and generates two frame pulse outputs, FP8o and FP16o, which are aligned to the master frame pulse. There is a constant throughput delay for data being switched from the input to the output of the device such that data which is input during Frame N is output during Frame N+2. For further details of frame pulse conditions and options, see Section 13.1, Control Register (CR), Figure 15, "Frame Boundary Conditions, ST-BUS Operation", and Figure 16, "Frame Boundary Conditions, GCI-Bus Operation".
FP8i C8i BSTi/LSTi0-7 (32 Mbps) FP8o C8o BSTo/LSTo0-7 (32 Mbps)
CH 01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 CH 01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
tFBOS
Figure 7 - Input and Output (Generated) Frame Pulse Alignment Figure 7 illustrates the input and output frame pulse alignment. The tFBOS is the offset between the input frame pulse, FP8i, and the generated output frame pulse, FP8o. Refer to the "AC Electrical Characteristics", on page 47. Note that although this figure shows the traditional setups of the frame pulses and clocks for both ST-BUS and
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Data Sheet
GCI-Bus configurations, the devices can be configured to accept/generate double-width frame pulses (if the FPW bit in the Control Register is set) as well as to use the opposite clock edge for frame-boundary determination (using the C8IPOL and COPOL bits in the Control Register). See the timing diagrams in "AC Electrical Characteristics", on page 47 for all of the available configurations.
2.4
Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator
To improve the jitter tolerance of the ZL50052, a Frame Boundary Discriminator (FBD) circuit was added to the device. This circuit is enabled by setting the Control Register bit FBDEN to HIGH. By default the FBD is disabled. The FBD can operate in two modes, as controlled by the FBD_MODE[2:0] bits of the Control Register. When bits FBD_MODE[2:0] are set to 000B, the FBD is set to handle lower frequency jitter only (<8 kHz). When bits FBD_MODE[2:0] are set to 111B, the FBD can handle both low frequency and high frequency jitter. All other values are reserved. These bits are ignored when bit FBDEN is LOW. It is strongly recommended that if bit FBDEN is set HIGH, bits FBD_MODE[2:0] should be set to 111B to improve the high frequency jitter handling capability. To achieve the best jitter tolerance performance, it is also recommended that the input data sampling point be optimized. In most applications, the optimum sampling point is 1/2 instead of the default 3/4 (it can be changed by programming all the LIDR and BIDR registers). This will give more allowance for sampling point variations caused by jitter. There are, however, some cases where data experiences more delay than the timing signals. A common example occurs when multiple data lines are tied together to form bi-directional buses. The large bus loading may cause data to be delayed. If this is the case, the optimum sampling point may be 3/4 or 4/4 instead of 1/2. The optimum sampling point is dependent on the application. The user should optimize the sampling point to achieve the best jitter tolerance performance.
2.5
Input Clock Jitter Tolerance
Jitter tolerance can not be accurately represented by just one number. Jitter of the same amplitude but different frequency spectrum can have different effect on the operation of a device. For example, a device that can tolerate 20 ns of jitter of 10 kHz frequency may only be able to tolerate 10ns of jitter of 1 MHz frequency. Therefore, jitter tolerance should be represented as a spectrum over frequency. The highest possible jitter frequency is half of the carrier frequency. In the case of the ZL50052, the input clock is 8.192 MHz, and the jitter associated with this clock can have the highest frequency component at 4.096 MHz. Tolerance of jitter of different frequencies are shown in the "AC Electrical Characteristics" section, table "Input Clock Jitter Tolerance" on page 54. The Jitter Tolerance Improvement Circuit was enabled (Control Register, bit FBDEN set HIGH, and bits FBD_MODE[2:0] set to 111B), and the sampling point was optimized.
3.0
Input and Output Offset Programming
Various registers are used to control the input sampling point (delay) and the output advancement for the Local and Backplane streams. The following sections explain the details of these offset programming features.
3.1
Input Offsets
Control of the Input Bit Delay allows each input stream to have a different frame boundary with respect to the master frame pulse, FP8i. Each input stream can be individually delayed by up to 7 3/4 bits with a resolution of 1/4 bit of the bit period.
3.1.1
Input Bit Delay Programming (Backplane and Local Input Streams)
Input Bit Delay Registers LIDR0 - 7 and BIDR0 - 7 work in conjunction with the SMPL_MODE bit in the Control Register to allow users to control input bit fractional delay as well as input bit sample point selection for greater flexibility when designing switch matrices for high speed operation.
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Data Sheet
When SMPL_MODE = LOW (input bit fractional delay mode) , bits LID[4:0] and BID[4:0] in the LIDR0 - 7 and BIDR0 - 7 registers respectively define the input bit fractional delay of the corresponding Local and Backplane stream. The total delay can be up to 7 3/4 bits with a resolution of 1/4 bit at the selected data rate. When SMPL_MODE = HIGH (sampling point select mode), bits LID[1:0] and BID[1:0] define the input bit sampling point of the stream. The sampling point can be programmed at the 3/4, 4/4, 1/4 or 2/4 bit location to allow better tolerance for input jitter. Bits LID[4:2] and BID[4:2] define the integer input bit delay, with a maximum value of 7 bits at a resolution of 1 bit. Refer to Figure 8 for Input Bit Delay Timing at 32 Mbps data rates. Refer to Figure 9 for Input Sampling Point Selection Timing at 32 Mbps data rates. SMPL_MODE = LOW
FP8i C8i
Ch511 Ch0 1 0 7 6 5 4 3 2 1 0 7 6 Ch1 5 4
BSTi/LSTi0-7 Bit Delay = 0 (Default) BSTi/LSTi0-7 Bit Delay = 1/4
3
2
Bit Delay, 1/4 Ch511 3 2 1 0 7 6 5 Ch0 4 3 2 1 0 7 6 Ch1 5 4
Bit Delay, 1/2
BSTi/LSTi0-7 Bit Delay = 1/2
Ch511 3 2 1 0 7 6 5
Ch0 4 3 2 1 0 7 6
Ch1 5 4
Bit Delay, 3/4
BSTi/LSTi0-7 Bit Delay = 3/4
Ch511 3 2 1 0 7 6 5
Ch0 4 3 2 1 0 7 6
Ch1 5 4
Bit Delay, 1 Ch511 Ch0 2 1 0 7 6 5 4 3 2 1 0 7 6 Ch1 5
BSTi/LSTi0-7 Bit Delay = 1
3
BSTi/LSTi0-7 Bit Delay = 7 1/2
Ch510 2 1 0 7 6 5
Ch511 4 3 2 1 0 7
Bit Delay, 7 1/2 Ch0 6 5 4
BSTi/LSTi0-7 Bit Delay = 7 3/4
Ch510 2 1 0 7 6 5
Ch511 4 3 2 1 0 7
Bit Delay, 7 3/4 Ch0 6 5 4
Please refer to Control Register (Section 13.1) for SMPL_MODE definition.
Figure 8 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 32 Mbps
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SMPL_MODE = LOW
FP8i C8i
Ch511 Ch0 0 7 6 5 4 3 2
Data Sheet
BSTi/LSTi0-7 BID[4:0]/LID[4:0] = 00000B Bit delay = 0 bit (Default)
1
sample at 3/4 point
BSTi/LSTi0-7 BID[4:0]/LID[4:0] = 00011B Bit Delay = 3/4 bit
Ch511 1 0 7
Ch0 6 sample at 3/4 point 5 4 3 2
SMPL_MODE = HIGH
FP8i C8i
Ch511 Ch0 0 7 6 sample at 3/4 point Ch511 Ch0 0 7 6 sample at 2/4 point 5 4 3 2 5 4 3 2
BSTi/LSTi0-7 BID[4:0]/LID[4:0] = 00000B 3/4 sampling (Default)
1
BSTi/LSTi0-7 BID[4:0]/LID[4:0] = 00011B 2/4 sampling
1
Please refer to Control Register (Section 13.1) for SMPL_MODE definition.
Figure 9 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for Data Rate of 32 Mbps
3.2
Output Advancement Programming (Backplane and Local Output Streams)
This feature is used to advance the output channel alignment of individual Local or Backplane output streams with respect to the frame boundary FP8o. Each output stream has its own advancement value that can be programmed by the Output Advancement Registers. The output advancement selection is useful in compensating for various parasitic loading on the serial data output pins. The Local and Backplane Output Advancement Registers, LOAR0 - LOAR7 and BOAR0 - BOAR7, are used to control the Local and Backplane output advancement respectively. The advancement is determined with reference to the internal system clock rate (131.072 MHz). The advancement can be 0, -1 cycle, -2 cycles or -3 cycles, which converts to approximately 0 ns, -7.6 ns, -15 ns or -23 ns as shown in Figure 10.
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Data Sheet
FP8o System Clock 131.072 MHz
Ch511 Bit Advancement, 0 Bit 0 Ch511 Bit 7 Bit Advancement, -1 Bit 0 Ch511 Bit 7 Bit Advancement, -2 Ch0 Bit 0 Ch511 Bit 7 Bit Advancement, -3 Bit 0 Bit 7 Bit 6 Bit 6 Ch0 Bit 5 Bit 4 Bit 5 Bit 4 Bit 6 Bit 6 Ch0 Bit 5 Ch0 Bit 5
BSTo/LSTo0-7 Bit Advancement = 0 (Default) BSTo/LSTo0-7 Bit Advancement = -1 BSTo/LSTo0-7 Bit Advancement = -2 BSTo/LSTo0-7 Bit Advancement = -3
Bit 1
Bit 1
Bit 1
Bit 1
Figure 10 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 32 Mbps
4.0
Port High-Impedance Control
The input pins, LORS and BORS, select whether the Local (LSTo0-7) and Backplane (BSTo0-7) output streams, respectively, are set to high impedance at the output of the device itself, or are always driven (active HIGH or active LOW). Setting LORS/BORS to a LOW state will configure the output streams, LSTo0-7/BSTo0-7, to transmit bi-state channel data. Setting LORS/BORS to a HIGH state will configure the output streams, LSTo0-7/BSTo0-7, of the device to invoke a high impedance output on a per-channel basis. The Local/Backplane Output Enable Bit (LE/BE) of the Local/Backplane Connection Memory has direct per-channel control on the high impedance state of the Local/Backplane output streams, L/BSTo0-7. Programming a LOW state in the connection memory LE/BE bit will set the stream output of the device to high impedance for the duration of the channel period. See "Local Connection Memory Bit Definition", on page 29 and "Backplane Connection Memory Bit Definition", on page 30 for programming details. The state of the LORS/BORS pin is detected and the device configured accordingly during a RESET operation, e.g., following power-up. The LORS/BORS pin is an asynchronous input and is expected to be hard-wired for a particular system application, although it may be driven under logic control if preferred. The Local/Backplane output enable control in order of highest priority is: RESET, ODE, OSB, LE/BE. LE/BE (Local / OSB LORS/BORS Backplane (Control (input pin) Register bit) Connection Memory bit) X X X X 0 X X X X X 0 1 0 1 0
RESET (input pin) 0 0 1 1 1
ODE (input pin) X X 0 0 1
LSTo0-7/ BSTo0-7 HIGH HI-Z HIGH HI-Z HIGH
Table 1 - Local and Backplane Output Enable Control Priority
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LE/BE OSB (Local / LORS/BORS (Control Backplane (input pin) Register bit) Connection Memory bit) 0 1 1 1 X 0 0 1 1 0 1 X
Data Sheet
RESET (input pin) 1 1 1 1
ODE (input pin) 1 1 1 1
LSTo0-7/ BSTo0-7 HI-Z HIGH HI-Z ACTIVE (HIGH or LOW)
Table 1 - Local and Backplane Output Enable Control Priority (continued)
5.0
Data Delay Through the Switching Paths
Serial data which goes into the device is converted into parallel format and written to consecutive locations in the data memory. Each data memory location corresponds to the input stream and channel number. Channels written to any of the buffers during Frame N will be read out during Frame N+2. The input bit delay and output bit advancement have no impact on the overall data throughput delay. In the following paragraphs, the data throughput delay (T) is represented as a function of ST-BUS frames, input channel number, (m), and output channel number (n). For 32.768 Mbps data rate, there are 512 channels on each stream. The input channel number (m) and output channel number (n) can therefore have a range of 0 to 511. The data throughput delay under various input channel and output channel conditions can be summarized as: T = 2 frames + (n - m) The data throughput delay (T) is: T = 2 frames + (n - m). Assuming that m (input channel) and n (output channel) are equal, we have the figure below, in which the delay between the input data being written and the output data being read is exactly 2 frames.
Frame Serial Input Data
Frame N
Frame N+1
Frame N+2
Frame N+3
Frame N+4
Frame N+5
Frame N Data
Frame N+1Data 2 Frames + 0
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
Frame N+5 Data
Serial Output Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
Figure 11 - Data Throughput Delay with Input Ch0 Switched to Output Ch0
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Data Sheet
Assuming that n (output channel) is greater than m (input channel), we have the figure below, in which the delay time between the input channel being written and the output channel being read exceeds 2 frames.
Frame Serial Input Data
Frame N
Frame N+1
Frame N+2
Frame N+3
Frame N+4
Frame N+5
Frame N Data
Frame N+1Data
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
Frame N+5 Data
2 Frames + (n - m)
Serial Output Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
Figure 12 - Data Throughput Delay with Input Ch0 Switched to Output Ch13 Assuming that n (output channel) is less than m (input channel), we have the figure below, in which the delay time between the input channel being written and the output channel being read is less than 2 frames.
Frame Serial Input Data
Frame N
Frame N+1
Frame N+2
Frame N+3
Frame N+4
Frame N+5
Frame N Data
Frame N+1Data
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
Frame N+5 Data
2 Frames + (n - m)
Serial Output Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
Figure 13 - Data Throughput Delay with Input Ch13 Switched to Output Ch0
6.0
Microprocessor Port
The 8 K switch family supports non-multiplexed Motorola type microprocessor buses. The microprocessor port consists of a 16-bit parallel data bus (D0-15), a 15-bit address bus (A0-14) and four control signals (CS, DS, R/W and DTA). The data bus provides access to the internal registers, the Backplane Connection and Data Memories, and the Local Connection and Data Memories. Each memory has 4,096 locations. See Table 5, Address Map for Data and Connection Memory Locations (A14 = 1), for the address mapping. Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can only be read (but not written) from the microprocessor port. To prevent the bus 'hanging', in the event of the switch not receiving a master clock, the microprocessor port shall complete the DTA handshake when accessed, but any data read from the bus will be invalid.
7.0
7.1
Device Power-Up, Initialization and Reset
Power-Up Sequence
The recommended power-up sequence is for the VDD_IO supply (nominally +3.3 V) to be established before the power-up of the VDD_PLL and VDD_CORE supplies (nominally +1.8 V). The VDD_PLL and VDD_CORE supplies may be powered-up simultaneously, but neither should 'lead' the VDD_IO supply by more than 0.3 V. All supplies may be powered-down simultaneously.
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7.2 Initialization
Data Sheet
Upon power-up, the device should be initialized by applying the following sequence: 1 2 Ensure the TRST pin is permanently LOW to disable the JTAG TAP controller. Set ODE pin to LOW. This sets the LSTo0-7 outputs to HIGH or high impedance, dependent on the LORS input value, and sets the BSTo0-7 outputs to HIGH or high impedance, dependent on BORS input value. Refer to Pin Description for details of the LORS and BORS pins. Reset the device by asserting the RESET pin to zero for at least two cycles of the input clock, C8i. A delay of an additional 250 s must also be applied before the first microprocessor access is performed following the de-assertion of the RESET pin; this delay is required for determination of the input frame pulse format. Use the Block Programming Mode to initialize the Local and the Backplane Connection Memories. Refer to Section 8.3, Connection Memory Block Programming. Set ODE pin to HIGH after the connection memories are programmed to ensure that bus contention will not occur at the serial stream outputs.
3
4 5
7.3
Reset
The RESET pin is used to reset the device. When set LOW, an asynchronous reset is applied to the device. It is then synchronized to the internal clock. During the reset period, depending on the state of input pins LORS and BORS, the output streams LSTo0-7 and BSTo0-7 are set to HIGH or high impedance, and all internal registers and counters are reset to the default state. The RESET pin must remain LOW for two input clock cycles (C8i) to guarantee a synchronized reset release. A delay of an additional 250 s must also be waited before the first microprocessor access is performed following the de-assertion of the RESET pin; this delay is required for determination of the frame pulse format. In addition, the reset signal must be de-asserted less than 12 s after the frame boundary or more than 13s after the frame boundary, as illustrated in Figure 14. This can be achieved, for example, by synchronizing the de-assertion of the reset signal with the input frame pulse FP8i.
FP8i RESET (case 1) RESET (case 2) 12 s RESET assertion 13 s RESET de-assertion
De-assertion of RESET must not fall within this window
Figure 14 - Hardware RESET De-assertion
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8.0 Connection Memory
Data Sheet
The device includes two connection memories, the Local Connection Memory and the Backplane Connection Memory.
8.1
Local Connection Memory
The Local Connection Memory (LCM) is a 16-bit wide memory with 4,096 memory locations to support the Local output port. The most significant bit of each word, bit[15], selects the source stream from either the Backplane (LSRC = LOW) or the Local (LSRC = HIGH) port and determines the Backplane-to-Local or Local-to-Local data routing. Bits[14:13] select the control modes of the Local output streams, the per-channel Message Mode and the per-channel high impedance output control modes. In Connection Mode (bit[14] = LOW), bits[12:0] select the source stream and channel number as detailed in Table 2. In Message Mode (bit[14] = HIGH), bits[12:8] are unused and bits[7:0] contain the message byte to be transmitted. Bit[13] must be HIGH for Message Mode to ensure that the output channel is not tri-stated.
8.2
Backplane Connection Memory
The Backplane Connection Memory (BCM) is a 16-bit wide memory with 4,096 memory locations to support the Backplane output port. The most significant bit of each word, bit[15], selects the source stream from either the Backplane (BSRC = HIGH) or the Local (BSRC = LOW) port and determines the Local-to-Backplane or Backplane-to-Backplane data routing. Bit[14:13] select the control modes of the Backplane output streams, namely the per-channel Message Mode and the per-channel high impedance output control mode. In Connection Mode (bit[14] = LOW), bits[12:0] select the source stream and channel number as detailed in Table 2. In Message Mode (bit[14] = HIGH), bits[12:8] are unused and bits[7:0] contain the message byte to be transmitted. Bit[13] must be HIGH for Message Mode to ensure that the output channel is not tri-stated. The Control Register bits MS[2:0] must be set to 000 to select the Local Connection Memory for the write and read operations via the microprocessor port. The Control Register bits MS[2:0] must be set to 001 to select the Backplane Connection Memory for the write and read operations via the microprocessor port. See Section 6.0, Microprocessor Port, and Section 13.1, Control Register (CR) for details on microprocessor port access. Source Stream Bit Rate 32 Mbps Source Stream No. Bits[12:9] legal values 0:7 Source Channel No. Bits[8:0] legal values 0:511
Table 2 - Local and Backplane Connection Memory Configuration
8.3
Connection Memory Block Programming
This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after power-up. When the Memory Block Programming mode is enabled, the contents of the Block Programming Register (BPR) will be loaded into the connection memories. See Table 11 and Table 12 for details of the Control Register and Block Programming Register values, respectively.
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8.3.1
* *
Data Sheet
Memory Block Programming Procedure
Set the MBP bit in the Control Register from LOW to HIGH. Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits, LBPD[2:0], of the Block Programming Register, will be loaded into bits[15:13] of the Local Connection Memory. The remaining bit positions are loaded with zeros as shown in Table 3. 15 LBPD2 14 LBPD1 13 LBPD0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Table 3 - Local Connection Memory in Block Programming Mode The Backplane Block Programming data bits, BBPD[2:0], of the Block Programming Register, will be loaded into bits[15:13] respectively, of the Backplane Connection Memory. The remaining bit positions are loaded with zeros as shown in Table 4. 15 BBPD2 14 BBPD1 13 BBPD0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Table 4 - Backplane Connection Memory in Block Programming Mode The Block Programming Register bit, BPE will be automatically reset LOW within 125 s, to indicate completion of memory programming. The Block Programming Mode can be terminated at any time prior to completion by clearing the BPE bit of the Block Programming Register or the MBP bit of the Control Register. Note that the default values (LOW) of LBPD[2:0] and BBPD[2:0] of the Block Programming Register, following a device reset, can be used. During reset, all output channels go HIGH or high impedance, depending on the value of the LORS and BORS pins, irrespective of the values in bits[14:13] of the connection memory.
9.0
Memory Built-In-Self-Test (BIST) Mode
As operation of the memory BIST will corrupt existing data, this test must only be instigated when the device is placed "out-of-service" or isolated from live traffic. The memory BIST mode is enabled through the microprocessor port (Section 13.7, Memory BIST Register). Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The memory test result is monitored through the Memory BIST Register.
10.0
JTAG Port
The ZL50052 JTAG interface conforms to the IEEE 1149.1 standard. The operation of the boundary-scan circuit shall be controlled by an external Test Access Port (TAP) Controller.
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10.1 Test Access Port (TAP)
Data Sheet
The Test Access Port (TAP) consists of four input pins and one output pin described as follows: * Test Clock Input (TCK) TCK provides the clock for the TAP Controller and is independent of any on-chip clock. TCK permits the shifting of test data into or out of the Boundary-Scan register cells under the control of the TAP Controller in Boundary-Scan Mode. Test Mode Select Input (TMS) The TAP controller uses the logic signals applied to the TMS input to control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin in internally pulled to VDD_IO when not driven from an external source. Test Data Input (TDi) Depending on the previously applied data to the TMS input, the serial input data applied to the TDi port is connected either to the Instruction Register or to a Test Data Register. Both registers are described in Section 10.2, TAP Registers. The applied input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to VDD_IO when not driven from an external source. Test Data Output (TDo) Depending on the previously applied sequence to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDo. The data out of the TDo is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo output is set to a high impedance state. Test Reset (TRST) TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled high when not driven from an external source. This pin MUST be pulled low for normal operation.
*
*
*
*
10.2
TAP Registers
The ZL50052 implements the public instructions defined in the IEEE-1149.1 standard with the provision of an Instruction Register and three Test Data Registers.
10.2.1
Test Instruction Register
The JTAG interface contains a 4-bit instruction register. Instructions are serially loaded into the Instruction Register from the TDi pin when the TAP Controller is in the shift-IR state. Instructions are subsequently decoded to achieve two basic functions: to select the Test Data Register to operate while the instruction is current, and to define the serial Test Data Register path to shift data between TDi and TDo during data register scanning. Please refer to Figure 24 for JTAG test port timing.
10.2.2 10.2.2.1
Test Data Registers The Boundary-Scan Register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the ZL50052 core logic.
10.2.2.2
The Bypass Register
The Bypass register is a single stage shift register to provide a 1-bit path from TDi to TDo.
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10.2.2.3 The Device Identification Register
Data Sheet
The JTAG device ID for the ZL50052 is 0C38414BH. Version, Bits <31:28>: 0000 Part No., Bits <27:12>: 1100 0011 1000 0100 Manufacturer ID, Bits <11:1>: 0001 0100 101 Header, Bit <0> (LSB): 1
10.3
Boundary Scan Description Language (BSDL) File
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the IEEE 1149.1 test interface.
11.0
Memory Address Mappings
When the most significant bit, A14, of the address bus is set to '1', the microprocessor performs an access to one of the device's internal memories. The Control Register bits MS[2:0] indicate which memory (Local Connection, Local Data, Backplane Connection, or Backplane Data) is being accessed. Address bits A0-A13 indicate which location within the particular memory is being accessed. Address Bit A14 Description Selects memory or register access (0 = register, 1 = memory) Note that which memory (Local Connection, Local Data, Backplane Connection, Backplane Data) is accessed depends on the MS[2:0] bits in the Control Register. Stream address (0 - 7) Streams 0 to 7 are used Channel address (0 - 511) Channels 0 to 511 are used when serial stream is at 32.768 Mbps Table 5 - Address Map for Data and Connection Memory Locations (A14 = 1) The device contains two data memory blocks, one for received Backplane data and one for received Local data. For all data rates, the received data is converted to parallel format by internal serial-to-parallel converters and stored sequentially in the relevant data memory.
A13-A9 A8-A0
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11.1 Local Data Memory Bit Definition
Data Sheet
The 8-bit Local Data Memory (LDM) has 4,096 positions. The locations are associated with the Local input streams and channels. As explained in the section above, address bits A13-A0 of the microprocessor define the addresses of the streams and the channels. The LDM is read-only and configured as follows: Bit 15:8 7:0 Name Reserved LDM Set to a default value of 8'h00. Local Data Memory - Local Input Channel Data The LDM[7:0] bits contain the timeslot data from the Local side input TDM stream. LDM[7] corresponds to the first bit received, e.g., bit 7 in ST-BUS mode, bit 0 in GCI-Bus mode. See Figure 6, "ST-BUS and GCI-Bus Input Timing Diagram" for the arrival order of the bits. Table 6 - Local Data Memory (LDM) Bits Note that the Local Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the table above are presented to provide 16-bit microprocessor read accesses. Description
11.2
Backplane Data Memory Bit Definition
The 8-bit Backplane Data Memory (BDM) has 4,096 positions. The locations are associated with the Backplane input streams and channels. As explained previously, address bits A13-A0 of the microprocessor define the addresses of the streams and the channels. The BDM is read-only and configured as follows: Bit 15:8 7:0 Name Reserved BDM Set to a default value of 8'h00. Backplane Data Memory - Backplane Input Channel Data. The BDM[7:0] bits contain the timeslot data from the Backplane side input TDM stream. BDM[7] corresponds to the first bit received, i.e. bit 7 in ST-BUS mode, bit 0 in GCI-Bus mode. See Figure 6, "ST-BUS and GCI-Bus Input Timing Diagram" for the arrival order of the bits. Table 7 - Backplane Data Memory (BDM) Bits Note that the Backplane Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the table above are presented to provide 16-bit microprocessor read accesses. Description
11.3
Local Connection Memory Bit Definition
The Local Connection Memory (LCM) has 4,096 addresses of 16-bit words. Each address, accessed through bits A13-A0 of the microprocessor port, is allocated to an individual Local output stream and channel. The bit definition for each 16-bit word is presented in Table 8 for Source-to-Local connections. The most-significant bit in the memory location, LSRC, selects the switch configuration for Backplane-to-Local or Local-to-Local. When the per-channel Message Mode is selected (LMM memory bit = HIGH), the lower byte of the LCM word (LCAB[7:0]) will be transmitted as data on the output stream (LSTo0-7) in place of data defined by the Source Control, Stream and Channel Address bits.
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Bit 15 Name LSRC Description
Data Sheet
Local Source Control Bit When LOW, the source is from the Backplane input port (Backplane Data Memory). When HIGH, the source is from the Local input port (Local Data Memory). Ignored when LMM is set HIGH. Local Message Mode Bit When LOW, the channel is in Connection Mode (data to be output on channel originated in Local or Backplane Data Memory). When HIGH, the channel is in Message Mode (data to be output on channel originated in Local Connection Memory). Local Output Enable Bit When LOW, the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the LORS pin. When HIGH, the channel is active. Source Stream Address Bits The binary value of these 4 bits represents the input stream number. Ignored when LMM is set HIGH. Source Channel Address Bits / Message Mode Data The binary value of these 9 bits represents the input channel number, when LMM is LOW. Bits LCAB[7:0] transmitted as data when LMM is set HIGH. Note: When LMM is set HIGH, in both ST-BUS and GCI-Bus modes, the LCAB[7:0] bits are output sequentially to the timeslot with LCAB[7] being output first. Table 8 - LCM Bits for Source-to-Local Switching
14
LMM
13
LE
12:9
LSAB[3:0]
8:0
LCAB[8:0]
11.4
Backplane Connection Memory Bit Definition
The Backplane Connection Memory (BCM) has 4,096 addresses of 16-bit words. Each address, accessed through bits A13-A0 of the microprocessor port, is allocated to an individual Backplane output stream and channel. The bit definition for each 16-bit word is presented in Table 9 for Source-to-Backplane connections. The most-significant bit in the memory location, BSRC, selects the switch configuration for Local-to-Backplane or Backplane-to-Backplane. When the per-channel Message Mode is selected (BMM memory bit = HIGH), the lower byte of the BCM word (BCAB[7:0]) will be transmitted as data on the output stream (BSTo0-7) in place of data defined by the Source Control, Stream and Channel Address bits.
Bit 15
Name BSRC
Description Backplane Source Control Bit When LOW, the source is from the Local input port (Local Data Memory). When HIGH, the source is from the Backplane input port (Backplane Data Memory). Ignored when BMM is set HIGH. Backplane Message Mode Bit When LOW, the channel is in Connection Mode (data to be output on channel originated in Backplane or Local Data Memory). When HIGH, the channel is in Message Mode (data to be output on channel originated in Backplane Connection Memory).
14
BMM
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Bit 13 Name BE Description
Data Sheet
Backplane Output Enable Bit When LOW, the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the BORS pin. When HIGH, the channel is active. Source Stream Address Bits The binary value of these 4 bits represents the input stream number. Ignored when BMM is set HIGH. Source Channel Address Bits / Message Mode Data The binary value of these 9 bits represents the input channel number, when BMM is LOW. Bits BCAB[7:0] transmitted as data when BMM is set HIGH. Note: When BMM is set HIGH, in both ST-BUS and GCI-Bus modes, the BCAB[7:0] bits are output sequentially to the timeslot with BCAB[7] being output first. Table 9 - BCM Bits for Source-to-Backplane Switching
12:9
BSAB[3:0]
8:0
BCAB[8:0]
12.0
Internal Register Mappings
When the most significant bit, A14, of the address bus is set to '0', the microprocessor is performing an access to one of the device's internal registers. Address bits A13-A0 indicate which particular register is being accessed. A14-A0 0000H 0001H 0023H - 002AH 0063H - 006AH 0083H - 008AH 00A3H - 00AAH 014DH 3FFFH Control Register, CR Block Programming Register, BPR Local Input Bit Delay Register 0 - 7, LIDR0 - 7 Backplane Input Bit Delay Register 0 - 7, BIDR0 - 7 Local Output Advancement Register 0 - 7, LOAR0 - 7 Backplane Output Advancement Register 0 - 7, BOAR0 - 7 Memory BIST Register, MBISTR Device Identification Register, DIR Table 10 - Address Map for Registers (A14 = 0) Register
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13.0 Detailed Register Descriptions
Data Sheet
This section describes the registers that are used in the device.
13.1
Control Register (CR)
Address 0000H. The Control Register defines which memory is to be accessed. It initiates the memory block programming mode and selects the Backplane and Local data rate modes. The Control Register (CR) is configured as follows: Bit 15:13 Name FBD_ MODE[2:0] Reset Value 0 Description Frame Boundary Discriminator Mode When set to 111B, the Frame Boundary Discriminator can handle both low frequency and high frequency jitter. When set to 000B, the Frame Boundary Discriminator is set to handle lower frequency jitter only. All other values are reserved. These bits are ignored when FBDEN bit is LOW. Sample Point Mode When LOW the input bit sampling point is always at the 3/4 bit location. The input bit fractional delay is programmed in 1/4 bit increments from 0 to 7 3/4 as per the value of the LIDR0 to LIDR7 and BIDR0 to BIDR7 registers. When HIGH, the input bit sampling point is programmed to the 3/4, 4/4, 1/4, 2/4 bit location as per the value of the LIDR0 to LIDR7 and BIDR0 to BIDR7 registers. In addition the incoming data can be delayed by 0 to 7 bits in 1 bit increments. See Table 13, Table 14, Table 15 and Table 16 for details. Reserved Must be set to 0 for normal operation Frame Boundary Discriminator Enable When LOW, the frame boundary discriminator function is disabled. When HIGH, enables frame boundary discriminator function which allows the device to tolerate inconsistent frame boundaries, hence improving the tolerance to cycle-to-cycle variation on the input clock. Reserved Must be set to 0 for normal operation Frame Pulse Width When LOW, the user must apply a 122 ns frame pulse on FP8i; the FP8o pin will output a 122 ns wide frame pulse; FP16o will output a 61 ns wide frame pulse. When HIGH, the user must apply a 244 ns frame pulse on FP8i; the FP8o pin will output a 244 ns wide frame pulse; FP16o will output a 122 ns wide frame pulse. Reserved Must be set to 0 for normal operation 8 MHz Input Clock Polarity The frame boundary is aligned to the falling or rising edge of the input clock. When LOW, the frame boundary is aligned to the clock falling edge. When HIGH, the frame boundary is aligned to the clock rising edge. Output Clock Polarity When LOW, the output clock has the same polarity as the input clock. When HIGH, the output clock is inverted. This applies to both the 8 MHz (C8o) and 16 MHz (C16o) output clocks. Table 11 - Control Register Bits
12
SMPL_ MODE
0
11 10
Reserved FBDEN
0 0
9 8
Reserved FPW
0 0
7 6
Reserved C8IPOL
0 0
5
COPOL
0
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Bit 4 Name MBP Reset Value 0 Description
Data Sheet
3
OSB
0
Memory Block Programming When LOW, the memory block programming mode is disabled. When HIGH, the connection memory block programming mode is ready to program the Local Connection Memory (LCM) and the Backplane Connection Memory (BCM). Output Stand By This bit enables the BSTo0-7 and LSTo0-7 serial outputs.
ODE Pin 0 1 1 OSB bit X 0 1 BSTo0-7, LSTo0-7 Disabled Disabled Enabled
Output Control with ODE pin and OSB bit When LOW, BSTo0-7 and LSTo0-7 are driven HIGH or high impedance, dependent on the BORS and LORS pin settings respectively. When HIGH, BSTo0-7 and LSTo0-7 are enabled. Reserved Must be set to 0 for normal operation Memory Select Bits These three bits select the connection or data memory for subsequent microport memory access operations: 00 selects Local Connection Memory (LCM) for read or write operations. 01 selects Backplane Connection Memory (BCM) for read or write operations. 10 selects Local Data Memory (LDM) for read-only operation. 11 selects Backplane Data Memory (BDM) for read-only operation. Table 11 - Control Register Bits (continued)
2 1:0
Reserved MS[1:0]
0 0
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Data Sheet
Frame Boundary
(a) Frame Pulse Width = 122 ns, Control Register Bit8 (FPW) = 0 Control Register Bit6 (C8IPOL) = 0
C8i FP8i
(b) Frame Pulse Width = 122 ns, Control Register Bit8 (FPW) = 0 Control Register Bit6 (C8IPOL) = 1
C8i FP8i
(c) Frame Pulse Width = 244 ns, Control Register Bit8 (FPW) = 1 Control Register Bit6 (C8IPOL) = 0
C8i FP8i
(d) Frame Pulse Width = 244 ns, Control Register Bit8 (FPW) = 1 Control Register Bit6 (C8IPOL) = 1
C8i FP8i
Figure 15 - Frame Boundary Conditions, ST-BUS Operation
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Data Sheet
Frame Boundary
(e) Pulse Width = 122 ns, Control Register Bit8 (FPW) = 0 Control Register Bit6 (C8IPOL) = 0
C8i FP8i
(f) Pulse Width = 122 ns, Control Register Bit8 (FPW) = 0 Control Register Bit6 (C8IPOL) = 1
C8i FP8i
(g) Pulse Width = 244 ns, Control Register Bit8 (FPW) = 1 Control Register Bit6 (C8IPOL) = 0
C8i FP8i
(h) Pulse Width = 244 ns, Control Register Bit8 (FPW) = 1 Control Register Bit6 (C8IPOL) = 1
C8i FP8i
Figure 16 - Frame Boundary Conditions, GCI-Bus Operation
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13.2 Block Programming Register (BPR)
Data Sheet
Address 0001H. The Block Programming Register stores the bit patterns to be loaded into the connection memories when the Memory Block Programming feature is enabled. The BPE, LBPD[2:0] and BBPD[2:0] bits in the BPR register must be defined in the same write operation. The BPE bit is set HIGH to commence the block programming operation. Programming is completed in one frame period and may be initiated at any time within a frame. The BPE bit returns to LOW to indicate that the block programming function has completed. When BPE is HIGH, no other bits of the BPR register may be changed for at least a single frame period, except to abort the programming operation. The programming operation may be aborted by setting either BPE to LOW, or the Control Register bit, MBP, to LOW. The BPR register is configured as follows.
.
Bit 15:7 6:4
Name Reserved BBPD[2:0]
Reset Value 0 0
Description Reserved Must be set to 0 for normal operation Backplane Block Programming Data These bits refer to the value loaded into the Backplane Connection Memory (BCM) when the Memory Block Programming feature is activated. When the MBP bit in the Control Register (CR) is set HIGH and BPE (in this register) is set HIGH, the contents of bits BBPD[2:0] are loaded into bits 15-13, respectively, of the BCM. Bits 12-0 of the BCM are set LOW. Local Block Programming Data These bits refer to the value loaded into the Local Connection Memory (LCM), when the Memory Block Programming feature is activated. When the MBP bit in the Control Register is set HIGH and BPE (in this register) is set HIGH, the contents of bits LBPD[2:0] are loaded into bits 15-13, respectively, of the LCM. Bits 12-0 of the LCM are set LOW. Block Programming Enable A LOW to HIGH transition of this bit enables the Memory Block Programming function. A LOW will be returned after 125 s, upon completion of programming. Set LOW to abort the programming operation. Table 12 - Block Programming Register Bits
3:1
LBPD[2:0]
0
0
BPE
0
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13.3 Local Input Bit Delay Registers (LIDR0 to LIDR7)
Data Sheet
Addresses 0023H to 002AH. There are 8 Local Input Delay Registers (LIDR0 to LIDR7). When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit location and LIDR0 to LIDR7 define the input bit and fractional bit delay of each Local stream. The possible bit delay adjustment is up to 7 3/4 bits, in steps of 1/4 bit. When the SMPL_MODE bit is HIGH, LIDR0 to LIDR7 define the input bit sampling point as well as the integer bit delay of each Local stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay can be adjusted in 1-bit increments from 0 to 7 bits. The LIDR0 to LIDR7 registers are configured as follows: LIDRn Bit
(where n = 0 to 7)
Name Reserved LID[4:0]
Reset Value 0 0
Description Reserved Must be set to 0 for normal operation Local Input Bit Delay Register When SMPL_MODE = LOW, the binary value of these bits refers to the input bit and fractional bit delay value (0 to 7 3/4). When SMPL_MODE = HIGH, the binary value of LID[1:0] refers to the input bit sampling point (1/4 to 4/4). LID[4:2] refers to the integer bit delay value (0 to 7 bits).
15:5 4:0
Table 13 - Local Input Bit Delay Register (LIDRn) Bits
13.3.1
Local Input Delay Bits 4-0 (LID[4:0])
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to sample each input. Input bit delay adjustment can range up to 7 3/4 bit periods forward, with resolution of 1/4 bit period. The default sampling point is at the 3/4 bit location. This can be described as: no. of bits delay = LID[4:0] / 4 For example, if LID[4:0] is set to 10011 (19), the input bit delay = 19 * 1/4 = 43/4. When SMPL_MODE = HIGH, the binary value of LID[1:0] refers to the input bit sampling point (1/4 to 4/4). LID[4:2] refers to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7 and that the sampling point can vary from 1/4 to 4/4 in 1/4 bit increments. Table 14 illustrates the bit delay and sampling point selection.
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LIDn SMPL_MODE = LOW LID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input Data Bit Delay 0 (Default) 1/4 1/2 3/4 1 1 1/4 1 1/2 1 3/4 2 2 1/4 2 1/2 2 3/4 3 3 1/4 3 1/2 3 3/4 4 4 1/4 4 1/2 4 3/4 5 5 1/4 5 1/2 5 3/4 6 6 1/4 6 1/2 6 3/4 7 7 1/4 7 1/2 7 3/4 SMPL_MODE = HIGH Input Data Bit Delay 0 (Default) 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7
Data Sheet
LID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
LID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
LID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Input Data Sampling Point 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4
Table 14 - Local Input Bit Delay and Sampling Point Programming Table
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13.4 Backplane Input Bit Delay Registers (BIDR0 to BIDR7)
Data Sheet
Addresses 0063H to 006AH There are 8 Backplane Input Delay Registers (BIDR0 to BIDR7). When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit location and BIDR0 to BIDR7 define the input bit and fractional bit delay of each Backplane stream. The possible bit delay adjustment is up to 7 3/4 bits, in steps of 1/4 bit. When the SMPL_MODE bit is HIGH, BIDR0 to BIDR7 define the input bit sampling point as well as the integer bit delay of each Backplane stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay can be adjusted in 1-bit increments from 0 to 7 bits. The BIDR0 to BIDR7 registers are configured as follows: BIDRn Bit
(where n = 0 to 7)
Name Reserved BID[4:0]
Reset Value 0 0
Description Reserved Must be set to 0 for normal operation Backplane Input Bit Delay Register When SMPL_MODE = LOW, the binary value of these bits refers to the input bit fractional delay value (0 to 7 3/4). When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point (1/4 to 4/4). BID[4:2] refers to the integer bit delay value (0 to 7 bits).
15:5 4:0
Table 15 - Backplane Input Bit Delay Register (BIDRn) Bits
13.4.1
Backplane Input Delay Bits 4-0 (BID[4:0])
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to sample each input. Input bit delay adjustment can range up to 7 3/4 bit periods forward, with resolution of 1/4 bit period. The default sampling point is at the 3/4 bit location. This can be described as: no. of bits delay = BID[4:0] / 4 For example, if BID[4:0] is set to 10011 (19), the input bit delay = 19 * 1/4 = 43/4. When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point (1/4 to 4/4). BID[4:2] refers to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7 and that the sampling point can vary from 1/4 to 4/4 in 1/4 bit increments.
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Table 16 illustrates the bit delay and sampling point selection. SMPL_MODE = LOW BID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input Data Bit Delay 0 (Default) 1/4 1/2 3/4 1 1 1/4 1 1/2 1 3/4 2 2 1/4 2 1/2 2 3/4 3 3 1/4 3 1/2 3 3/4 4 4 1/4 4 1/2 4 3/4 5 5 1/4 5 1/2 5 3/4 6 6 1/4 6 1/2 6 3/4 7 7 1/4 7 1/2 7 3/4 SMPL_MODE = HIGH Input Data Bit Delay 0 (Default) 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7
Data Sheet
BIDn
BID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
BID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
BID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Input Data Sampling Point 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4
Table 16 - Backplane Input Bit Delay and Sampling Point Programming Table
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13.5 Local Output Advancement Registers (LOAR0 to LOAR7)
Data Sheet
Addresses 0083H to 008AH. 8 Local Output Advancement Registers (LOAR0 to LOAR7) allow users to program the output advancement for output data streams LSTo0 to LSTo7. The possible adjustment is -1 (7.6 ns), -2 (15 ns) or -3 (23 ns) cycles of the internal system clock (131.072 MHz). The LOAR0 to LOAR7 registers are configured as follows: LOARn Bit
(where n = 0 to 7)
Name Reserved LOA[1:0]
Reset Value 0 0
Description Reserved Must be set to 0 for normal operation Local Output Advancement Value
15:2 1:0
Table 17 - Local Output Advancement Register (LOAR) Bits
13.5.1
Local Output Advancement Bits 1-0 (LOA1-LOA0)
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal alignment with the generated frame pulse FP8o. Corresponding Advancement Bits LOA1 0 0 1 1 LOA0 0 1 0 1
Local Output Advancement Clock Rate 131.072 MHz 0 (Default) -1 cycle (~7.6 ns) -2 cycles (~15 ns) -3 cycles (~23 ns)
Table 18 - Local Output Advancement (LOAR) Programming Table
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13.6 Backplane Output Advancement Registers (BOAR0 - BOAR7)
Data Sheet
Addresses 00A3H to 00AAH 8 Backplane Output Advancement Registers (BOAR0 to BOAR7) allow users to program the output advancement for output data streams BSTo0 to BSTo7. The possible adjustment is -1 (7.6 ns), -2 (15 ns) or -3 (23 ns) cycles of the internal system clock (131.072 MHz). The BOAR0 to BOAR7 registers are configured as follows: BOARn Bit
(where n = 0 to 7)
Name Reserved BOA[1:0]
Reset Value 0 0
Description Reserved Must be set to 0 for normal operation Backplane Output Advancement Value
15:2 1:0
Table 19 - Backplane Output Advancement Register (BOAR) Bits
13.6.1
Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal alignment with the generated frame pulse FP8o. Corresponding Advancement Bits BOA1 0 0 1 1 BOA0 0 1 0 1
Backplane Output Advancement Clock Rate 131.072 MHz 0 (Default) -1 cycle (~7.6 ns) -2 cycles (~15 ns) -3 cycles (~23 ns)
Table 20 - Backplane Output Advancement (BOAR) Programming Table
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13.7 Memory BIST Register
Data Sheet
Address 014DH. The Memory BIST Register enables the self-test of chip memory. Two consecutive write operations are required to start MBIST: the first with only bit 12 (LV_TM) set HIGH (i.e. 1000h); the second with bit 12 maintained HIGH but with the required start bit(s) also set HIGH. The MBISTR register is configured as follows: Reset Value 0 0
Bit 15:13 12
Name Reserved LV_TM
Description Reserved Must be set to 0 for normal operation MBIST Test Enable Set HIGH to enable MBIST mode. Set LOW for normal operation. Backplane Data Memory Start BIST Sequence Sequence enabled on LOW to HIGH transition. Backplane Data Memory BIST Sequence Completed (Read-only) This bit must be polled - when HIGH, indicates completion of Backplane Data Memory BIST sequence. Backplane Data Memory Pass/Fail Bit (Read-only) This bit indicates the Pass/Fail status following completion of the Backplane Data Memory BIST sequence (indicated by assertion of BISTCDB). A HIGH indicates Pass, a LOW indicates Fail. Local Data Memory Start BIST Sequence Sequence enabled on LOW to HIGH transition. Local Data Memory BIST Sequence Completed (Read-only) This bit must be polled - when HIGH, indicates completion of Local Data Memory BIST sequence. Local Data Memory Pass/Fail Bit (Read-only) This bit indicates the Pass/Fail status following completion of the Local Data Memory BIST sequence (indicated by assertion of BISTCDL). A HIGH indicates Pass, a LOW indicates Fail. Backplane Connection Memory Start BIST Sequence Sequence enabled on LOW to HIGH transition. Backplane Connection Memory BIST Sequence Completed (Read-only) This bit must be polled - when HIGH, indicates completion of Backplane Connection Memory BIST sequence. Backplane Connection Memory Pass/Fail Bit (Read-only) This bit indicates the Pass/Fail status following completion of the Backplane Connection Memory BIST sequence (indicated by assertion of BISTCCB). A HIGH indicates Pass, a LOW indicates Fail. Table 21 - Memory BIST Register (MBISTR) Bits
11 10
BISTSDB BISTCDB
0 0
9
BISTPDB
0
8 7
BISTSDL BISTCDL
0 0
6
BISTPDL
0
5 4
BISTSCB BISTCCB
0 0
3
BISTPCB
0
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Bit 2 1 Name BISTSCL BISTCCL Reset Value 0 0 Description Local Connection Memory Start BIST Sequence Sequence enabled on LOW to HIGH transition.
Data Sheet
Local Connection Memory BIST Sequence Completed (Read-only) This bit must be polled - when HIGH, indicates completion of Local Connection Memory BIST sequence. Local Connection Memory Pass/Fail Bit (Read-only) This bit indicates the Pass/Fail status following completion of the Local Connection Memory BIST sequence (indicated by assertion of BISTCCL). A HIGH indicates Pass, a LOW indicates Fail.
0
BISTPCL
0
Table 21 - Memory BIST Register (MBISTR) Bits (continued)
13.8
Device Identification Register
Address 3FFFH. The Device Identification Register stores the binary value of the silicon revision number and the Device ID. This register is read-only. The DIR register is configured as follows: Bit 15:8 7:4 3 2:0 Name Reserved RC[3:0] Reserved DID[2:0] Reset Value 0 0000 0 101 Description Reserved Will be set to 0 in normal operation Revision Control Bits Reserved Will be set to 0 in normal operation Device ID
Table 22 - Device Identification Register (DIR) Bits
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14.0 DC Electrical Characteristics
Data Sheet
Absolute Maximum Ratings* Parameter 1 2 3 4 5 6 7 8 Core Supply Voltage I/O Supply Voltage PLL Supply Voltage Input Voltage (non-5 V tolerant inputs) Input Voltage (5 V tolerant inputs) Continuous Current at digital outputs Package power dissipation Storage temperature Symbol VDD_CORE VDD_IO VDD_PLL VI VI_5V Io PD TS - 55 Min. -0.5 -0.5 -0.5 -0.5 -0.5 Max. 2.5 5.0 2.5 VDD_IO +0.5 7.0 15 1.5 +125 Units V V V V V mA W C
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions Characteristics 1 2 3 4 5 6 Operating Temperature Positive Supply Positive Supply Positive Supply Input Voltage Input Voltage on 5 V Tolerant Inputs Sym. TOP VDD_IO VDD_CORE VDD_PLL VI VI_5V Min. -40 3.0 1.71 1.71 0 0 Typ. 25 3.3 1.8 1.8 Max. +85 3.6 1.89 1.89 VDD_IO 5.5 Units C V V V V V
Voltages are with respect to ground (VSS) unless otherwise stated.
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DC Electrical Parameters Characteristics 1a I 1b N 1c 1d P U T 2 3 4 S Input High Voltage Input Low Voltage Input Leakage (input pins) Input Leakage (bi-directional pins) Weak Pullup Current 5 6 7 8 9 O U T P U T S Weak Pulldown Current Input Pin Capacitance Output High Voltage Output Low Voltage High-Impedance Leakage VIH VIL IIL IBL IPU IPD CI VOH VOL IOZ 2.4 0.4 5 2.0 0.8 5 5 200 200 5 V V A A A A pF V V A Supply Current Supply Current Supply Current Supply Current Sym. IDD_Core IDD_Core IDD_IO IDD_IO 14 240 Min. Typ. Max. 4 290 100 18 Units. mA mA A mA
Data Sheet
Test Conditions Static IDD_Core and PLL current Applied clock C8i = 8.192 MHz Static IDD_IO IAV with all output streams at max. data rate unloaded
0 < V < VDD_IO Note 1 Input at 0 V Input at VDD_IO IOH = 8 mA IOL = 8 mA 0 < V0 < VDD_IO Note 1
10 Output Pin Capacitance CO 5 pF Voltages are with respect to ground (Vss) unless otherwise stated. Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V).
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15.0 AC Electrical Characteristics
Data Sheet
AC Electrical Characteristics Timing Parameter Measurement: Voltage Levels Characteristics 1 2 3 CMOS Threshold Rise/Fall Threshold Voltage High Rise/Fall Threshold Voltage Low Sym. VCT VHM VLM Level 0.5 VDD_IO 0.7 VDD_IO 0.3 VDD_IO Units V V V Conditions 3.0 V < VDD_IO < 3.6 V 3.0 V < VDD_IO < 3.6 V 3.0 V < VDD_IO < 3.6 V
Input and Output Clock Timing Characteristic 1 2 3 4 5 6 7 8 FP8i, Input Frame Pulse Width Input Frame Pulse Setup Time (before C8i clock falling/rising edge) Input Frame Pulse Hold Time (from C8i clock falling/rising edge) C8i Clock Period (Average value, does not consider the effects of jitter) C8i Clock Pulse Width High C8i Clock Pulse Width Low C8i Clock Rise/Fall Time C8i Cycle to Cycle Variation (This values is with respect to the typical C8i Clock Period, and using mid-bit sampling) Output Frame Boundary Offset FP8o Frame Pulse Width Sym. tIFPW244 tIFPW122 tIFPS244 tIfPS122 tIFPH244 tIFPH122 tICP tICH tICL trIC, tfIC tCCVIC Min. 210 10 5 5 0 0 120 50 50 0 -7.0 122 61 61 2 Typ. 244 122 Max. 350 220 110 60 110 60 124 70 70 3 7.0 Units ns ns ns ns ns ns ns ns Notes
9 10
tOFBOS tOFPW8_244 tOFPW8_122 tFPFBF8_244 tFPFBF8_122 tFBFPF8_244 tFBFPF8_122 tOCP8 tOCH8 tOCL8 trOC8, tfOC8 224 117 117 58 117 58 117 58 58 3
7 244 122 122 61 122 61 122 61 61
9.5 264 127 127 64 127 64 127 64 64 7
ns ns FPW = 1 FPW = 0 CL = 60 pF FPW = 1 FPW = 0 CL = 60 pF FPW = 1 FPW = 0 CL = 60 pF CL = 60 pF
11
FP8o Output Delay (from frame pulse edge to output frame boundary) FP8o Output Delay (from output frame boundary to frame pulse edge) C8o Clock Period C8o Clock Pulse Width High C8o Clock Pulse Width Low C8o Clock Rise/Fall Time
ns
12
ns
13 14 15 16
ns ns ns ns
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Input and Output Clock Timing (continued) Characteristic 17 FP16o Frame Pulse Width Sym. tOFPW16_122 tOFPW16_61 tFPFBF16_122 tFPFBF16_61 tFBFPF16_122 tFBFPF16_61 tOCP16 tOCH16 tOCL16 trOC16, tfOC16 Min. 117 58 58 29 58 29 58 29 29 3 Typ. 122 61 61 31 61 31 61 31 31 Max. 127 64 64 33 64 33 64 33 33 7 Units ns
Data Sheet
Notes FPW = 1 FPW = 0 CL = 60 pF FPW = 1 FPW = 0 FPW = 1 FPW = 0
18
FP16o Output Delay (from frame pulse edge to output frame boundary) FP16o Output Delay (from output frame boundary to frame pulse edge) C16o Clock Period C16o Clock Pulse Width High C16o Clock Pulse Width Low C16o Clock Rise/Fall Time
ns
19
ns
20 21 22 23
ns ns ns ns CL= 60 pF
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Zarlink Semiconductor Inc.
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Data Sheet
tIFPW244 FP8i (244 ns) tIFPS244 tIFPW122 tIFPH244
FP8i (122 ns) tIFPS122 tICL C8i tICH
tIFPH122 tICP
trIC
tfIC
CK_int * tOFBOS FP8o (244 ns) tFPFBF8_244
tOFPW8_122
tOFPW8_244
tFBFPF8_244
FP8o (122 ns) tFPFBF8_122 tOCL8 C8o trOC8 tOFPW16_122 FP16o (122 ns) tFPFBF16_122 tOFPW16_61 FP16o (61 ns) tFPFB16_61 tOCL16 C16o trOC16 tfOC16 tOCH16 tFBFP16_61 tOCP16 tFBFPF16_122 tfOC8 tOCH8 tFBFPF8_122 tOCP8
Note *: CK_int is the internal clock signal of 131.072 MHz. Note **: Although the figures above show the frame boundary as measured from the falling edge of C8i/C8o/C16o, the frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the Control Register.
Figure 17 - Input and Output Clock Timing Diagram for ST-BUS
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Data Sheet
FP8i (244 ns) tIFPS244 FP8i (122 ns) tIFPS122 tICL C8i tICH tIFPW122
tIFPW244
tIFPH244
tIFPH122 tICP
trIC
tfIC
CK_int * tOFBOS FP8o (244 ns) tFPFBF8_244
tOFPW8_122
tOFPW8_244
tFBFPF8_244
FP8o (122 ns) tFPFBF8_122 tOCL8 tOCH8 tFBFPF8_122 tOCP8
C8o
trOC8 tOFPW16_122 FP16o (122 ns) tFPFBF16_122 tOFPW16_61 FP16o (61 ns) tFPFB16_61 tOCH16 C16o tfOC16 tOCL16 tFBFP16_61 tOCP16 tFBFPF16_122
tfOC8
trOC16
Note *: CK_int is the internal clock signal of 131.072 MHz. Note **: Although the figures above show the frame boundary as measured from the rising edge of C8i/C8o/C16o, the frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the Control Register.
Figure 18 - Input and Output Clock Timing Diagram for GCI-Bus
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Local and Backplane Data Timing Characteristic 1 Local/Backplane Input Data Sampling Point Sym. tIDS32 Min. 20 Typ. 23 Max. 26 Units ns
Data Sheet
Notes With SMPL_MODE = 0 (3/4-bit sampling) and zero offset. With respect to Min. Input Data Sampling Point With respect to Max. Input Data Sampling Point
2
Local/Backplane Serial Input Set-up Time
tSIS32
2
ns
3
Local/Backplane Serial Input Hold Time
tSIH32
2
ns
4 5
Output Frame Boundary Offset Local/Backplane Serial Output Delay
tOFBOS tSOD32
7
9.5 4.5
ns ns CL= 50 pF These numbers are referencing output frame boundary.
FP8i C8i CK_int * tIDS32 tSIS32 tSIH32 L/BSTi0-7 32.768 Mbps
2 1 0 7 6 5 4 3 2
tOFBOS FP8o C8o CK_int * tSOD32 L/BSTo0-7 32.768 Mbps
Bit1 Ch511 Bit1 Ch511 Bit0 Ch511 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0 Bit3 Ch0 Bit2 Ch0
Note *: CK_int is the internal clock signal of 131.072 MHz.
Figure 19 - ST-BUS Local/Backplane Data Timing Diagram (32 Mbps)
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Data Sheet
FP8i C8i CK_int * tIDS32 tSIS32 tSIH32 L/BSTi0-7 32.768 Mbps
2 1 0 7 6 5 4 3 2
tOFBOS FP8o C8o CK_int * tSOD32 L/BSTo0-7 32.768 Mbps
Bit5 Ch511 Bit6 Ch511 Bit7 Ch511 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0 Bit4 Ch0 Bit5 Ch0
Note *: CK_int is the internal clock signal of 131.072 MHz.
Figure 20 - GCI-Bus Local/Backplane Data Timing Diagram (32 Mbps)
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Local and Backplane Output High-Impedance Timing Characteristic 1 STo delay - Active to High-Z - High-Z to Active Output Driver Enable (ODE) Delay to Active Data Output Driver Enable (ODE) Delay to High-Impedance Sym. tDZ tZD tODE tODZ Min. Typ. 4 4 Max. 6 6 Units ns ns
Data Sheet
Test Conditions RL = 1k, CL = 50 pF, See Note 1
2
14 14
ns ns
RL = 1 k, CL = 50 pF, See Note 1 RL 1 k, CL = 50 pF, See Note 1
Note 1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL .
CLK tDZ STo Valid Data tZD STo HiZ
VTT
HiZ
VTT
Valid Data
VTT
Figure 21 - Serial Output and External Control
VTT ODE tODE tODZ VTT
STo
Hi-Z
Valid Data
Hi-Z
Figure 22 - Output Driver Enable (ODE)
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Zarlink Semiconductor Inc.
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Input Clock Jitter Tolerance Jitter Frequency 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 kHz 10 kHz 50 kHz 66 kHz 83 kHz 95 kHz 100 kHz 200 kHz 300 kHz 400 kHz 500 kHz 1 MHz 2 MHz 4 MHz 32.768 Mbps Data Rate Jitter Tolerance 600 600 80 50 35 30 20 14 14 14 14 14 14 14 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Data Sheet
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Zarlink Semiconductor Inc.
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Non-Multiplexed Microprocessor Port Timing Characteristics 1 2 3 4 5 6 7 CS setup from DS falling R/W setup from DS falling Address setup from DS falling CS hold after DS rising R/W hold after DS rising Address hold after DS rising Data setup from DTA Low on Read Sym. tCSS tRWS tADS tCSH tRWH tADH tRDS Min. 0 9 9 0 9 9 5 12 4.5 Typ. Max. Units ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions
Memory Read Register Read CL = 60 pF CL = 60 pF, RL = 1 k Note 1
8
Data hold on read
tRDH
9 10 11
Data setup on write Data hold on write Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory Acknowledgment Hold Time
tWDS tWDH tAKD
9 9 88 80
ns ns ns ns ns CL = 60 pF CL = 60 pF CL= 60 pF, RL = 1 k, Note 1
12
tAKH
11
Note 1: Note 2:
High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge CL. There must be a minimum of 30 ns between CPU accesses, to allow the device to recognize the accesses as separate (i.e., a minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion of CS and/or DS to initiate the next access).
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Data Sheet
DS tCSS CS tRWS R/W tADS A0-A14
VALID ADDRESS
tCSH
VTT
VTT tRWH VTT tADH VTT tRDH
D0-D15 READ tWDS D0-D15 WRITE
VALID READ DATA
VTT tWDH
VALID WRITE DATA
VTT
tRDS
DTA
VTT tAKD tAKH
Figure 23 - Motorola Non-Multiplexed Bus Timing
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AC Electrical Characteristics - JTAG Test Port Timing Characteristic 1 2 3 4 5 6 7 8 9 TCK Clock Period TCK Clock Pulse Width High TCK Clock Pulse Width Low TMS Set-up Time TMS Hold Time TDi Input Set-up Time TDi Input Hold Time TDo Output Delay TRST pulse width Sym. tTCKP tTCKH tTCKL tTMSS tTMSH tTDIS tTDIH tTDOD tTRSTW 200 Min. 100 80 80 10 10 20 60 30 Typ. Max. Units ns ns ns ns ns ns ns ns ns
Data Sheet
Notes
CL = 30 pF
Characteristics are over recommended operating conditions unless otherwise stated.
tTCKL TCK
tTCKH
tTCKP
tTMSS TMS
tTMSH
tTDIS tTDIH TDi
tTDOD TDo
tTRSTW TRST
Figure 24 - JTAG Test Port Timing Diagram
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Zarlink Semiconductor Inc.
J
TOP VIEW
DIMENSION MIN MAX A 1.35 (1.55) 1.75 (1.97) A1 0.30 0.50 A2 0.75 0.85 D 15.00 BSC 13.70 D1 12.95 E 15.00 BSC E1 13.70 12.95 1.0 REF. I J 1.0 REF. 0.40 0.60 b 1.00 BSC e N 196 2 LAYERS (4 LAYERS)
I
BOTTOM VIEW
Conforms to JEDEC MS - 034 Except dimensions 'A1' and 'b'.
NOTES:1. Controlling dimensions are in MM. 2. Seating plane is defined by the spherical crown of the solder balls. 3. Not to scale. 4. Ball arrangement: 14 x 14 array
SIDE VIEW
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes:
ISSUE ACN DATE APPRD.
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